Semiconductor integrated circuit

ABSTRACT

When an input signal to be amplified is very small and a large blocking signal having a high frequency is included in an input, it is necessary for a filter for mobile communication for removing thereof that a common-mode signal rejection ratio is large. Further, even in the case of an amplifier having a high gain, it is preferable that the common-mode rejection ratio is large in order to avoid saturation of the amplifier by noise. A common-mode rejecting characteristic is added to an input stage by making transconductance circuits of an input of an integrating circuit proposed by Nauta differential circits and connecting thereof in cross connection. Thereby, a filter as well as an amplifier improving the common-mode rejection ratio of a total, are realized by being applied to a CMOS process or a BiCMOS process.

TECHNICAL FIELD

The present invention relates to a semiconductor integrated circuitexcellent in a common-mode rejection ratio for improving a common-moderejection ratio of a circuit of an integrated amplifier, integrator,filter or the like.

BACKGROUND ART

Balanced signal processing (differential signal processing) is one ofcircuit technologies effective in being used for increasing a dynamicrange of an analog block. The differential signal processing is not onlyprovided with high capability of rejecting common-mode noise such aspower source coupling, blocking signal inputted in a common mode butalso provided with various advantages in comparison with an unbalancedtype signal processing such as restraint of harmonic components at evennumber orders or flexibility in design.

However, in designing a differential type circuit, feedback for adifferential signal does not effect influence on an output of acommon-mode component and consequently, a common-mode signal stays in anopen loop and an output potential is not determined. Therefore, in orderto maintain a common-mode output voltage at certain reference voltage,other negative feedback loop must be included in a common-mode signalpath so that the level of the common-mode output voltage is fixed to thepotential.

Generally, it is difficult to design the newly added feedback loop forthe common-mode signal, depending on cases, the circuit may be broughtinto an unstable state. In order to resolve the problem, there have beenproposed several circuits which does not use the feedback loop for acommon-mode signal. As a representative conventional example, there ispointed out B. Nauta, “A CMOS transconductance-C filter technique forvery high frequencies”, IEEE J. Solid-State Circuits vol.27, No.2 pp.142-153, February 1992. FIG. 2 shows an integrator for a filter proposedby Nauta. Although a detailed description will be given later of theoperation principle, according to the circuit, a common-mode componentcannot be rejected completely and the common-mode rejection ratio isrestricted even in an ideal state in which a variation in elements isnot included.

DISCLOSURE OF INVENTION

When an input signal to be amplified is very small, there is includedlarge blocking signal having a high frequency in an input and there isconstituted a filter for mobile communication for rejecting thereof,suppression of the blocking signal becomes insufficient when thecommon-mode signal rejection ratio is small. Further, in considerationof constituting an amplifier having a high gain, in order to avoidsaturation by common-mode noise, it is necessary to improve thecommon-mode rejection ratio. From the above-described, it is a problemof the present invention to realize a differential circuit forsignificantly reducing a common-mode gain.

In order to achieve the above-described problem, according to thepresent invention, transconductance circuits of an input of anintegrating circuit proposed by Nauta are made to be differentialcircuits and are connected in cross connection. Thereby, there can beadded a common-mode rejection characteristic at an input stage and thecommon-mode rejection ratio of a total is improved.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a basic block diagram of a first embodiment according to thepresent invention,

FIG. 2 is a block diagram showing an integrator to which a conventionaldifferential transconductance circuit is applied,

FIG. 3 is a general block diagram for inputting and outputtingdifferential signals,

FIG. 4 is a block diagram of the first embodiment of the presentinvention having a feedback circuit by transconductance,

FIG. 5 is a block diagram showing an integrator to which the firstembodiment of the present invention is applied,

FIG. 6 is a block diagram showing the integrator according to the firstembodiment of the present in which a feedback circuit is constituted bytransistors and resistors,

FIG. 7 is a block diagram of a second embodiment according to thepresent invention in which a filter is fed back,

FIG. 8 is a circuit diagram showing widely-known CMOSOTA used forverifying by a simulation of the second embodiment of the presentinvention,

FIG. 9 is a block diagram of a third embodiment of the present inventionin which a leap-frog type low-pass filter is fed back,

FIG. 10 is a circuit diagram showing a BiCMOS differential 2 inputintegrator applied to the third embodiment of the present invention,

FIG. 11 is a block diagram showing a leap-frog type low-pass filteraccording to a fourth embodiment constituted by feeding back respectiveintegrators,

FIG. 12 is a block diagram showing a BiCMOS differential 2 inputintegrator having a feedback circuit applied to the fourth embodiment ofthe present invention,

FIG. 13 is a block diagram of a receiving circuit for mobilecommunication and a diagram showing a relationship between received waveand blocking signal at respective stage,

FIG. 14 is a block diagram showing filters according to a fifthembodiment of the present invention,

FIG. 15 is a circuit diagram of a first order low-pass filter applied tothe fifth embodiment of the present invention,

FIG. 16 is a block diagram showing a second order notch filter appliedto the fifth embodiment of the present invention,

FIG. 17 is a circuit diagram showing a first order high-pass filterapplied to the fifth embodiment of the present invention and

FIG. 18 is a circuit diagram showing an all-pass filter applied to thefifth embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

A detailed explanation will be given of specific embodiments of thepresent invention in reference to the drawings as follows.

Notations in the drawings are as follows.

Numerals 11 and 12 designate input terminals, numerals 13 and l4designate output terminals, numerals 21 and 22 designate inputterminals, numerals 23 and 24 designate output terminals, numeral 25designates a single end transconductor g_(m1), numeral 26 designates adetailed circuit of a signal end transconductor, numeral 27 designates asingle end transconductor g_(m2A), numeral 28 designates a single endtransconductor g_(m2B), numerals 31 and 32 designate input terminals,numerals 33 and 34 designate output terminals, numerals 41 and 42designate input terminals, numerals 43 and 44 designate outputterminals, numeral 45 designates a load impedance Z_(f), numeral 46designates a differential input single output transconductor g_(m13A),numeral 47 designates a differential input single output transconductorg_(m13B), numerals 48 and 49 designate sums of output current, numeral40 designates a transfer function T₁₁, numeral 51 designates adifferential input single output transconductor g_(m2A), numeral 52designates a differential input single output transconductor g_(m2B),numeral 53 designates a capacitor, numerals 61 and 62 designateresistors, numeral 63 designates a transistor, numeral 71 designates adifferential input single output transconductor g_(m4A), numeral 72designates a differential input single output transconductor g_(m4B),numerals 73 and 74 designate nodes, numerals 81 and 82 designate inputterminals, numeral 83 designates an output terminal, numeral 84designates ground potential VSS, numeral 85 designates power sourcepotential VDD, numerals 91 and 92 designate one end groundeddifferential input terminals, numerals 93 and 94 designate adifferential input terminal pair, numeral 95 designates a differential3input transconductor, numerals 101, 102, 103, 104 designatedifferential input terminals, numeral 105 designates a single outputterminal, numerals 106, 107, 108, 109 designate bias control terminals,numeral 1101 designates a differential 3input transconductor, numeral1102 designates a differential 2 input transconductor, numerals 1103 and1104 designate input terminals, numerals 1105 and 1106 designate outputterminals, numeral 1201 designates a coupling resistor, numeral 1202designates a transistor, numeral 1203 designates a differential 2 inputtransconductor, numeral 1301 designates an antenna, numeral 1302designates a received signal, numeral 1303 designates an in-bandblocking signal, numeral 1304 designates an off-band blocking signal,numeral 1305 designates a first bandpass filter, numeral 1306 designatesa low noise amplifier, numeral 1307 designates a first band pass filter,numeral 1308 designates a mixer circuit, numeral 1309 designates anintermediate frequency band pass filter, numeral 1310 designates amodulator, numeral 1311 designates an I signal, numeral 1312 designatesa Q signal, numeral 1313 designates a base band filter circuit, numeral1401 designates a first order low-pass filter, numeral 1402 designates asecond order notch filter, numeral 1403 designates a first orderhigh-pass filter, numeral 1404 designates a third order leap-frog typelow-pass filter, numeral 1405 designates a first order all-pass filter,numeral 1501 designates a signal source impedance, numeral 1502designates a resistor, numeral 1503 designates a capacitor, numeral 1504designates a buffer amplifier, numeral 1701 designates a differentialoperational amplifier, numeral 1702 designates a buffer amplifier,numerals 1703 and 1704 designate resistors, numeral 1705 designates acapacitor, numeral 1801 designates a transconductor, numeral 1802designates a buffer amplifier and numeral 1803 designates a capacitor.

An explanation will be given of a first embodiment of the presentinvention in reference to FIGS. 1, 2, 3, 4, 5 and 6. First, consider acircuit shown by FIG. 3 in order to investigate a general circuit havinga symmetrical structure. FIG. 3 shows a circuit of 2 inputs and 2outputs in which inputs are designated by numerals 31 and 32 (v_(in1),v_(in2)) and outputs are designated by numerals 33 and 34 (v_(out1),v_(out2)). The outputs v_(out1) and v_(out2) are represented as followsby using inputs v_(in2) and v_(in2) also in consideration of feedbacktherefrom. $\begin{matrix}{v_{out1} = {{T_{11}\quad v_{in1}} + {T_{12}\quad v_{in2}} + {T_{13}\quad v_{out1}} + {T_{14}\quad v_{out2}}}} & \left( {{Equation}\quad 1} \right) \\{v_{out2} = {{T_{21}\quad v_{in1}} + {T_{22}\quad v_{in2}} + {T_{23}\quad v_{out1}} + {T_{24}\quad v_{out2}}}} & \left( {{Equation}\quad 2} \right)\end{matrix}$

In these equations, notation T_(ij) designates transfer functions frominput or output to respective outputs. There are derived conditions forconstituting respectively desired transfer characteristics by transfercharacteristic with regard to differential components and common-modecomponents. First, based on the above-described equations, there iscalculated a characteristic with regard to a differential signal.Differential output voltage v_(outd)=v_(out1)−v_(out2), becomes asfollows from (Equation 1) and (Equation 2). $\begin{matrix}{v_{outd} = {{\left( {T_{11} - T_{21}} \right)\quad v_{in1}} + {\left( {T_{12} - T_{22}} \right)\quad v_{in2}} + {\left( {T_{13} - T_{23}} \right)\quad v_{out1}} + {\left( {T_{14} - T_{24}} \right)\quad v_{out2}}}} & \left( {{Equation}\quad 3} \right)\end{matrix}$

In this case, in order that v_(outd) becomes a function of onlydifferential input voltage v_(ind)=v_(in2)−v_(in2), the followingrelationships are needed. $\begin{matrix}{{T_{11} - T_{21}} = {{- T_{12}} + T_{22}}} & \left( {{Equation}\quad 4} \right) \\{{T_{13} - T_{23}} = {{- T_{14}} + T_{24}}} & \left( {{Equation}\quad 5} \right)\end{matrix}$

At this occasion, (Equation 3) becomes as follows. $\begin{matrix}{v_{outd} = {{v_{out1} - v_{out2}} = {\frac{T_{11} - T_{21}}{1 - T_{13} + T_{23}}\quad v_{ind}}}} & \left( {{Equation}\quad 6} \right)\end{matrix}$

Next, a characteristic with regard to a common-mode signal iscalculated. Common-mode output voltage v_(outc)=v_(out1)+v_(out2)becomes as follows from (Equation 1) and (Equation 2). $\begin{matrix}{v_{outc} = {{\left( {T_{11} + T_{21}} \right)\quad v_{in1}} + {\left( {T_{12} + T_{22}} \right)\quad v_{in2}} + {\left( {T_{13} + T_{23}} \right)\quad v_{out1}} + {\left( {T_{14} + T_{24}} \right)\quad v_{out2}}}} & \left( {{Equation}\quad 7} \right)\end{matrix}$

In this case, in order that v_(outc) is constituted by a function ofonly common-mode input voltage v_(inc)=v_(in1)+v_(in2), the followingrelationships are needed. $\begin{matrix}{{T_{11} + T_{21}} = {T_{12} + T_{22}}} & \left( {{Equation}\quad 8} \right) \\{{T_{13} + T_{23}} = {T_{14} + T_{24}}} & \left( {{Equation}\quad 9} \right)\end{matrix}$

At this occasion, (Equation 7) becomes as follows. $\begin{matrix}{v_{outc} = {{v_{out1} + v_{out2}} = {\frac{T_{11} + T_{21}}{1 - T_{13} - T_{23}}\quad v_{inc}}}} & \left( {{Equation}\quad 10} \right)\end{matrix}$

When all of (Equation 4), (Equation 5), (Equation 8) and (Equation 9)are established, there are derived equivalent conditions as follows.$\begin{matrix}{{T_{11} = T_{22}},{T_{12} = T_{21}},{T_{13} = T_{24}},{T_{14} = T_{23}}} & \left( {{Equation}\quad 11} \right)\end{matrix}$

Here, as an example, consider to realize a differential filter. In thedifferential filter, it is preferable that a common-mode signal outputis null. Hence, in order that a transfer function from the common-modeinput signal v_(inc) to the common-mode output signal v_(outc), is null,the following relationship must be established. $\begin{matrix}{T_{11} = {{- T_{21}}\quad \left( {= {T_{22} = {- T_{12}}}} \right)}} & \left( {{Equation}\quad 12} \right)\end{matrix}$

Further, in order that a characteristic from the differential inputsignal V_(ind) to the differential output signal V_(outd) is constitutedby a desired transfer function T₀, (Equation 13) may be satisfied asfollows. $\begin{matrix}{\frac{T_{11} - T_{21}}{1 - T_{13} + T_{23}} = {\frac{2\quad T_{11}}{1 - T_{13} + T_{23}} = T_{0}}} & \left( {{Equation}\quad 13} \right)\end{matrix}$

Further, when the following relationship is established for simplicity,$\begin{matrix}{T_{13} = T_{23}} & \left( {{Equation}\quad 14} \right)\end{matrix}$

the following relationship is established. $\begin{matrix}{{2\quad T_{11}} = T_{0}} & \left( {{Equation}\quad 15} \right)\end{matrix}$

By substituting (Equation 11), (Equation 12) and (Equation 14) which arecondition equations in which common-mode output voltage does not appearand in which differential output voltage is a function of onlydifferential input voltage, for (Equation 1) and (Equation 2), theoutputs v_(out1) and v_(out2) are as follows. $\begin{matrix}{{v_{out1} = {{T_{11}\quad \left( {v_{in1} - v_{in2}} \right)} + {T_{13}\quad \left( {v_{out1} + v_{out2}} \right)}}},} & \left( {{Equation}\quad 16} \right) \\{v_{out2} = {{T_{11}\quad \left( {v_{in2} - v_{in1}} \right)} + {T_{13}\quad \left( {v_{out1} + v_{out2}} \right)}}} & \left( {{Equation}\quad 17} \right)\end{matrix}$

From the above-described, FIG. 1 is provided as a total block diagram.

In constituting the circuits, a condition for stabilizing the circuit isindispensable other than (Equation 11), (Equation 12) and (Equation 14).There are derived equations showing the conditions that the differentialcircuit structure of FIG. 1 is stable. When there are calculatedtransfer characteristics from respective inputs 11 and 12 to outputs 13and 14 (v_(out1), v_(out2)) based on (Equation 1) and (Equation 2), thefollowing relationships are established. $\begin{matrix}{v_{out1} = \frac{{T_{A}\quad v_{in1}} + {T_{B}\quad v_{in2}}}{{\left( {1 - T_{13}} \right)\quad \left( {1 - T_{24}} \right)} - {T_{14}\quad T_{23}}}} & \left( {{Equation}\quad 18} \right) \\{v_{out2} = \frac{{T_{C}\quad v_{in1}} + {T_{D}\quad v_{in2}}}{{\left( {1 - T_{13}} \right)\quad \left( {1 - T_{24}} \right)} - {T_{14}\quad T_{23}}}} & \left( {{Equation}\quad 19} \right)\end{matrix}$

In these equations, notations T_(A), T_(B), T_(C) and T_(D) arerepresented as follows. $\begin{matrix}\begin{matrix}{{T_{A} = \quad {T_{11} - {T_{11}\quad T_{24}} + {T_{14}\quad T_{21}}}},} \\{{T_{B} = \quad {T_{12} - {T_{12}\quad T_{24}} + {T_{14}\quad T_{22}}}},} \\{{T_{C} = \quad {T_{21} - {T_{21}\quad T_{13}} + {T_{23}\quad T_{11}}}},} \\{T_{D} = \quad {T_{22} - {T_{22}\quad T_{13}} + {T_{23}\quad T_{12}}}}\end{matrix} & \left( {{Equation}\quad 20} \right)\end{matrix}$

At this occasion, respective T_(ij) is designed to satisfy the followingrelationships which are in relationships of sufficient conditions withregard to (Equation 11) and (Equation 12). $\begin{matrix}{T_{11} = {T_{22} = {{- T_{12}} = {{- T_{21}} = \frac{N_{11}}{D_{A}}}}}} & \left( {{Equation}\quad 21} \right) \\{T_{13} = {T_{24} = {T_{14} = {T_{23} = \frac{N_{13}}{D_{B}}}}}} & \left( {{Equation}\quad 22} \right)\end{matrix}$

Incidentally, N₁₁, N₁₃, D_(A) and D_(B) are polynomials of Laplacianvariable s. When the sufficient conditions are substituted for (Equation18) and (Equation 19), the following relationships are provided.$\begin{matrix}{{v_{out1} = {{\frac{N_{11}\quad \left( {D_{B} - {2\quad N_{13}}} \right)\quad v_{in1}}{D_{A}\quad \left( {D_{B} - {2\quad N_{13}}} \right)} - \frac{N_{11}\quad \left( {D_{B} - {2\quad N_{13}}} \right)\quad v_{in2}}{D_{A}\quad \left( {D_{B} - {2\quad N_{13}}} \right)}} = {\frac{N_{11}}{D_{A}}\quad \left( {v_{in1} - v_{in2}} \right)}}},} & \left( {{Equation}\quad 23} \right) \\{{v_{out2} = {{\frac{{- N_{11}}\quad \left( {D_{B} - {2\quad N_{13}}} \right)\quad v_{in1}}{D_{A}\quad \left( {D_{B} - {2\quad N_{13}}} \right)} + \frac{N_{11}\quad \left( {D_{B} - {2\quad N_{13}}} \right)\quad v_{in2}}{D_{A}\quad \left( {D_{B} - {2\quad N_{13}}} \right)}} = {\frac{- N_{11}}{D_{A}}\quad \left( {v_{in1} - v_{in2}} \right)}}},} & \left( {{Equation}\quad 24} \right)\end{matrix}$

From these equations, the condition that the circuit of FIG. 1 isstable, resides in satisfying conditions of Hurwitz polynomial in whichreal parts of Eigen values of D_(A) and D_(B)−2N₁₃ become negative.Notation D_(A) designates a denominator polynomial of a desired transferfunction and accordingly is Hurwitz polynomial. Therefore, when(D_(B)−2N₁₃) is selected to be Hurwitz polynomial, the differentialcircuit of FIG. 1 is stable.

A further detailed description will be given of a method of realizingthe circuit of FIG. 1. Various differential circuits can be derived fromthe circuit structure of FIG. 1. A degree of freedom is constituted in away of selecting the function T₁₃, and accordingly, a performance and acircuit scale of a total circuit differ by what function is selected.FIG. 4 shows a constitution example realizing T₁₃ by two of OTAs(Operational Transconductance Amplifier, hereinafter, abbreviated asOTA). In FIG. 4, notation T₁₁ designates a transfer function from plusand minus input terminals 41 and 42 to output nodes 43 and 44. NotationZ_(f) designates a transimpedance 45 from sums 48 and 49 (i_(oj)(j=1,2))of output currents of transconductances 46 (g_(m13A)) and 47 (g_(m13B))to the output nodes 43 and 44. In this case, T₁₃ is given as −Z_(f)g_(m)when g_(m13A)=g_(m13B)=g_(m).

In an integrated circuit, element values of elements having the samestructure excellently coincide with each other, however, more or lessmismatch is produced by a process condition. (Equation 16) and (Equation17) show that when the element values are completely matched, that is,transfer functions T₁₁ and T₁₃ in the two equations coincide with eachother, the common-mode gain becomes null.

An investigation will be given of an influence when the mismatch isproduced in the transfer function. (Equation 16) and (Equation 17) aremodified and rewritten as follows. $\begin{matrix}{{v_{out1} = {{T_{11}\quad \left( {v_{in1} - v_{in2}} \right)} + {T_{13}\quad \left( {v_{out1} + v_{out2}} \right)}}},} & \left( {{Equation}\quad 25} \right) \\{v_{out2} = {{T_{11p}\quad \left( {v_{in2} - v_{in1}} \right)} + {T_{13p}\quad \left( {v_{out1} + v_{out2}} \right)}}} & \left( {{Equation}\quad 26} \right)\end{matrix}$

In these equations, T_(11p) and T_(13p) in (Equation 26) show that anerror is included in the transfer function. The common-mode outputvoltage v_(outc)=v_(out1)+v_(out2), becomes as follows from (Equation25) and (Equation 26). $\begin{matrix}{v_{outc} = {{\frac{T_{11} - T_{11p}}{1 - T_{13} - T_{13p}}\quad \left( {v_{in1} - v_{in2}} \right)} = {\frac{T_{11} - T_{11p}}{1 - T_{13} - T_{13p}}\quad v_{ind}}}} & \left( {{Equation}\quad 27} \right)\end{matrix}$

Here, based on the constitution example of FIG. 4, when respectives ofT₁₃ and T_(13p) are defined as follows, $\begin{matrix}{\begin{matrix}{{T_{13} = {{- Z_{f}}\quad g_{m13}}},} \\{{g_{m13} > 0},}\end{matrix}\quad \begin{matrix}{{T_{13p} = {{- Z_{f}}\quad g_{m13p}}},} \\{g_{m13p} > 0}\end{matrix}} & \left( {{Equation}\quad 28} \right)\end{matrix}$

v_(outc) becomes as follows. $\begin{matrix}{v_{outc} = {\frac{T_{11} - T_{11p}}{1 + {Z_{f}\left( {g_{m13} + g_{m13p}} \right)}}v_{ind}}} & \text{(Equation~~29)}\end{matrix}$

As is apparent from (Equation 29), when T₁₁≠T_(11p), the common-modeoutput voltage v_(outc) does not become null. When there is not afeedback circuit, from (Equation 16) and (Equation 17), even when T₁₃=0,the common-mode output voltage v_(outc) becomes null and therefore, wheng_(m3)=g_(m3p)=0, v_(outc) becomes as follows. $\begin{matrix}{v_{outc} = {\left( {T_{11} - T_{11p}} \right)v_{ind}}} & \text{(Equation~~30)}\end{matrix}$

For example, when a constitution of an integrator is considered, T₁₁ andT_(11p) are realized to provide very large gains in direct current andtherefore, a direct current differential component significantly changesthe common-mode output component and normally, output is saturated.Meanwhile, for example, even in the case of mismatch, from (Equation29), when g_(m13) and g_(m13p) are increased, the common-mode outputvoltage is monotonously reduced. Therefore, even when there is mismatchin element values constituting T₁₁ and T_(11p) and the common-mode gaindoes not become null, by a feedback loop constituted by T₁₃, thecommon-mode component can sufficiently be reduced.

FIG. 5 shows a circuit constitution in the case of connecting acapacitor 53 and constituting an integrator based on the constitutionexample of FIG. 4. The transfer functions T₁₁ and T₁₃ in this case arerespectively as follows when g_(m2A)=g_(m2B)=g_(m2) with regard to thetransconductances 51 and 52 (g_(m2A), g_(m2B)). $\begin{matrix}{{T_{11} = \frac{g_{m1}}{{sC}_{1}}},{T_{13} = {- \frac{g_{m2}}{{sC}_{1}}}}} & \text{(Equation~~31)}\end{matrix}$

A detailed description will be given of a difference between the circuitconstitution of the present invention shown in FIG. 4 and that of theconventional example shown in FIG. 2. Both are provided with feedbackloops constituted by g_(m2A) and g_(m2B) similarly and the effect isalso the same. A difference therebetween resides in that OTA on theinput side are provided with two inputs and there is outputted currentin proportion to voltage between input terminals. By connecting theinputs in cross connection, the common-mode input signals are canceledby each other. In order to show the difference, there is calculated atransfer function from an input signal to an output signal according tothe conventional example of FIG. 2. First, for simplicity, wheng_(m1)=g_(m2A)=g_(m2B)=g_(m), the outputs v_(out1) or v_(out2) arerepresented as follows. $\begin{matrix}{v_{out1} = {{- \frac{g_{m}}{sC}}\left( {v_{inc} + \frac{v_{ind}}{2} + v_{out1} + v_{out2}} \right)}} & \text{(Equation~~32)} \\{v_{out2} = {{- \frac{g_{m}}{sC}}\left( {v_{inc} - \frac{v_{ind}}{2} + v_{out1} + v_{out2}} \right)}} & \text{(Equation~~33)}\end{matrix}$

From (Equation 32) and (Equation 33), the differential output voltagev_(outd) and the common-mode output voltage v_(outc) become as follows.$\begin{matrix}{v_{outd} = {{v_{out1} - v_{out2}} = {{- \frac{g_{m}}{sC}}v_{ind}}}} & \text{(Equation~~34)} \\{v_{outc} = {{v_{out1} + v_{out2}} = {{- \frac{2g_{m}}{{sC} + {2g_{m}}}}v_{inc}}}} & \text{(Equation~~35)}\end{matrix}$

As is apparent from (Equation 35), according to the differentialintegrator circuit of FIG. 2, the transfer function from the common-modeinput signal v_(inc), to the common-mode output signal v_(outc) is notnull and therefore, a common-mode component of the input is outputted.

In FIG. 5, self feedback of g_(m2A) can be realized by one resistor andwhen influence of base current of the transistor and emitter resistancethereof are disregarded because of a voltage control current source,g_(m2B) can be realized by a single resistor and a single transistor.

FIG. 6 shows a circuit constitution in which g_(m2A) and g_(m2B)constituting T₁₃ are replaced by a resistor and a transistor. Accordingto the circuit constitution of FIG. 6, two transistors 63 constitute adifferential negative impedance converter and when g_(m2A)=g_(m2B), thenegative resistor 61 (1/g_(m2A)) of OTA and negative resistance−1/g_(m2B) generated by the transistor 63, are canceled by each other.Thereby, there can be realized an integrator improving the common-moderejection ratio by a simple element constitution in accordance with theembodiment. Further, the circuit of the embodiment can also be used as avoltage amplifier by replacing load not by a capacitor but by aresistor.

A description will be given of a second embodiment according to thepresent invention in reference to FIGS. 7 and 8. In this case, considerto realize a filter circuit having a large common-mode rejection ratioby designating a transfer function of a filter by notation T₁₁.

From (Equation 15), T₀=2T₁₁ and therefore, when a filter is constitutedby setting the integrator as T₁₁, a value of g_(m) is doubled and bythat amount, a capacitor necessary for providing the same time constantis also doubled. In contrast thereto, when the transfer function of thefilter is directly realized as T₁₁, the filter transfer function isdoubled and therefore, although direct current gain of the filter isincreased by 6 dB, a capacitance value necessary for realizing the samefilter transfer function is halved in comparison with that in the caseof constituting the integrator as T₁₁.

Further, whereas there is needed OTA for realizing T₁₃ for respectiveintegrator according to the constitution of FIG. 5, when the filtertransfer function is directly realized as T₁₁, the filter can beconstituted by a smaller number of OTA.

FIG. 7 shows a differential second order low-pass filter with a secondorder filter as a basic building block. Even when a sum i0j (j=1,2) ofoutput currents of transconductances 71 and 72 (g_(m4A) and g_(m4B))constituting T₁₃, is connected to either of nodes 73 and 74, the effectas T₁₃ stays almost the same and therefore, in this case, aninvestigation will be given in the case in which the sum is connected tothe node 74, that is, to an output terminal of the filter.

First, the stability is investigated. In FIG. 7, wheng_(m4A)=g_(m4B)=g_(m4), T₁₃ is calculated as follows. $\begin{matrix}{T_{13} = {\frac{N_{13}}{D_{B}} = \frac{{{- C_{1}}g_{m4}s} - {g_{m2}g_{m4}}}{{C_{1}C_{2}s^{2}} + {C_{2}g_{m2}s} + {g_{m2}g_{m3}}}}} & \text{(Equation~~36)}\end{matrix}$

D_(B) is the same as D_(A) and therefore, D_(B) is always Hurwitzpolynomial. Therefore, with regard to D_(B)−2N₁₃ for determining thestability of the filter, a consideration may be given only to influenceeffected by g_(m) ₄ capable of being provided with an arbitrary value.D_(B)−2N₁₃ is found to be always stable since with regard to arbitrarypositive g_(m4), D_(B)−2N₁₃ is a second order polynomial of Laplacianvariable having only a positive coefficient.

In FIG. 7, a differential output signal and a low-pass output areprovided respectively from nodes A and B. As OTA, as shown by FIG. 8, aconventionally-known CMOS transistor having differential voltage inputs81 and 82 and single current output 83, is applicable and a differentialtransconductor is applicable.

When a value of transconductance g_(m) of all of OTA is set to 39.52μA/V and a capacitance value is set to 10 pF, there can be provided asecond order filter having a cutoff frequency of 630 kHz and a Q valueof 1. When a simulation is carried out by applying a device constant ofa standard 1.2μCMOS process, there is achieved a common-mode rejectionratio equal to or larger than 60 dB in a pass band and the effectivenessof the embodiment is confirmed.

An explanation will be given of a third embodiment of the presentinvention in reference to FIGS. 9 and 10. FIG. 9 shows an example ofapplying a third order leap-frog type low-pass filter to T₁₁. In thedrawing, a multi-input transconductor 95 is provided with threedifferential inputs. Numerals 93 and 94 designate a set of differentialpair and numerals 91 and 92 designate ends on one side of differentialinputs grounding respective pair of terminals.

FIG. 10 shows a specific circuit of a differential 2 input integrator asan example of a multi-input integrator. In this case, there is applied aprocess mixed with bipolar transistors and CMOS transistors. Numerals101 and 102 constitute a first set of differential input terminals, andnumerals 103 and 104 constitute a second set of differential inputterminals. Numeral 105 designate a current output terminal and numerals106 through 109 designate bias control terminals.

When a simulation is carried out by applying a device constant of aBiCMOS process of 0.6 μm, there is achieved a common-mode rejectionratio of 52 dB. Further, also when Monte Carlo method is applied and aresistance value in the circuit is dispersed by ±1% uncorrelatedly,there is achieved a common-mode rejection ratio equal to or larger than42 dB. By the embodiment, there is realized the filter circuit achievinga large common-mode rejection ratio even when there is present adispersion among elements.

An explanation will be given of a fourth embodiment of the presentinvention in reference to FIGS. 11 and 12. According to the embodiment,different from the second and the third embodiments, there is applied anintegrator introduced in the first embodiment and feedback is providedto respective integrator constituting a filter.

FIG. 11 shows a total constitution of a filter. Signals are inputtedfrom terminal pair 1103 and 1104 and outputs are taken from terminalpair 1105 and 1106. The filter is constituted by one 6 input integrator(differential 3 input) 1101 and two 4 input integrator (differential 2input) 1102.

The 4 input integrator is shown in FIG. 12. According thereto, two ofintegrators 1203 introduced in FIG. 10 of the third embodiment, areapplied and feedback circuits are added. A feedback loop is added withan emitter coupling resistor 1201 and a transistor 1202 in diodeconnection for correcting impedance of the transistor based on thecircuit constituted by a transistor and a resistor shown by FIG. 6.

Similar to the third embodiment, when a simulation is carried out byapplying a device constant of BiCMOS process of 0.6 μm, there isachieved a common-mode rejection ratio equal to or larger than 105 dB inpass band. Further, even when Monte Carlo method is applied and aresistance value in the circuit is dispersed by ±1% uncorrelatedly,there is achieved a common-mode rejection ratio equal to or larger than85 dB. According to the embodiment, the feedback is provided to therespective integrator and therefore, in comparison with the second andthe third embodiments, although a circuit scale is enlarged, anexcellent common-mode rejection ratio can be achieved.

An explanation will be given of a fifth embodiment of the presentinvention in reference to FIGS. 13 through 18. The embodiment realizes abase band filter for mobile communication. An explanation will be givenof an outline of a signal processing at a receiving circuit in referenceto FIG. 13. A signal inputted from an antenna 1301 includes not only areceived signal 1302 but also an unnecessary blocking signal. Theblocking signal includes an in-band blocking signal 1303 caused by thesame application operation generated in a received frequency band and anoff-band blocking signal 1304 by other application such as publicbroadcasting, business wireless or the like.

The signal inputted from the antenna passes through a first band-passfilter 1305. At this occasion, the off-band blocking signal isattenuated. The signal is amplified by a low noise amplifier 1306 andthereafter passes through a second band-pass filter 1307. Also in thiscase, only the off-band blocking signal is attenuated and the in-bandblocking signal passes therethrough without being attenuated. The signalis converted into an intermediate frequency signal by a mixer circuit1308 and thereafter passes through an intermediate frequency band-passfilter 1309. In this case, the off-band blocking signal is furtherattenuated and the in-band blocking signal is attenuated to some degree.

The signal is separated into an I signal 1311 and a Q signal 1312 by amodulator 1310. At this occasion, the received signal is included infrom DC to a frequency of a half of an occupied band width and a signalof a frequency higher than the above-described frequency constitutes theunnecessary blocking signal. The intensity of the blocking signal in thebase band may be that of a signal equal to or larger than 50 dB andrejection of the gigantic blocking signal poses a serious problem. Sucha large signal is inputted to the received signal and therefore, it canbe understood that a base band filter circuit 1313 needs to achieve asufficiently large common-mode rejection ratio with allowance.

FIG. 14 shows a filter constitution of the embodiment. The constitutionof the filter is constructed by a series connection of a first orderlow-pass filter (including output buffer amplifier) 1401, a second ordernotch filter 1402, a first order high-pass filter 1403, a third orderleap-frog type low-pass filter 1404 and a first order all-pass filter1405. Transfer functions of respective portions are, for example, asfollows when normalized by a pass band frequency. $\begin{matrix}{{{T_{int}(s)} = \frac{1}{s + 1}}{{T_{notch}(s)} = \frac{0.0884817\quad \left( {S^{2} + 11.578} \right)}{S^{2} + {0.548325s} + 1.02445}}{{T_{diff}(s)} = {0.5\left( {1 - s} \right)}}{{T_{leapfrog}(s)} = \frac{0.1560886\quad \left( {S^{2} + 4.42243} \right)}{\left( {S^{2} + {1.6754s} + 1.19563} \right)\quad \left( {s + 1.15469} \right)}}{{T_{all}(s)} = \frac{1 - s}{s + 1}}} & \text{(Equation~~37)}\end{matrix}$

Here, notations T_(int), T_(notch), T_(diff), T_(leapfrog) and T_(all)respectively designate transfer functions of the first order low-passfilter (including output buffer amplifier), the second order notchfilter, the first order high-pass filter, the third order leap-frog typelow-pass filter and the first order all-pass filter.

As shown by FIG. 15, the first order low-pass filter is constituted by asignal source impedance 1501, a resistor 1502 and a capacitor 1503.Since the filter is a passive element, even when a signal having a largeamplitude is inputted, the signal is not distorted. Further, since thesignal having the large amplitude is a blocking signal having a highfrequency, the signal can efficiently be attenuated by the first orderfilter and an amplitude of an input signal at a successive stage can bereduced. There is provided a buffer amplifier 1504 such that the timeconstant of the first order filter is not influenced by other circuitand the signal is transmitted to the successive stage.

The second order notch filter is provided for making steep attenuationat outside of a band of the base band signal. FIG. 16 shows an exampleof the constitution. There is adopted a constitution similar to those ofthe second and the third embodiments in which the transfer function ofthe filter is made to correspond to T₁₁.

The first order high-pass filter is connected successively. FIG. 17shows an example of a circuit constitution. The filter is constituted bya differential operational amplifier 1701 and a buffer amplifier 1702,resistors 1703 and 1704 and a capacitor 1705. These are provided tocancel a variation in a cutoff frequency caused by a valuation in anelement value of the first order low-pass filter at the initial stage.Therefore, it is necessary to use constituent elements of the resistorsand the capacitor having structures the same as those of the first orderlow-pass filter. The circuit according to the third embodiment isapplicable to the third order leap-frog type low-pass filter.

FIG. 18 shows an example of a constitution of the all-pass filter at thefinal stage. The all-pass filter is used for correcting a phasevariation in the pass band. A minus polarity input terminal and anoutput terminal of OTA1801 are connected and used as a resistor. By theresistor and capacitors 1803 for controlling the phase, there isprovided a circuit characteristic in which an amplitude characteristicis constant and the phase is changed. Buffer amplifiers 1802 areprovided at circuit outputs to thereby reduce an influence effected on afilter time constant of a circuit at a successive stage.

When the above-described circuits are designed by assumedly setting thecutoff frequency to 1.25 MHz and a simulation is carried out by applyinga device constant of a BiCMOS process of 0.6 μm similar to the thirdembodiment, there is provided a result of a maximum pass-band gain of 0dB, an attenuation amount at 1.25 MHz of 2.92 dB, an attenuation amountat 2.5 MHz of 50.1 dB, a group delay variation of 0.17 μsec, acommon-mode rejection ratio of 120 dB or more and a maximum inputamplitude of 450 mV or more and the effectiveness of the embodiment isconfirmed.

According to the invention, there can be realized the filter as well asthe amplifier significantly improving the common-mode rejection ratio.The effect of improvement is confirmed in either of the cases orapplying thereof to the CMOS process and the BiCMOS process by thesimulation and the effect is confirmed also in the case of including thevariation in elements.

Industrial Applicability

As has been described above, the semiconductor integrated circuitaccording to the present invention is useful as a circuit used in asystem of transmitting a signal of a filter, an integrator, an amplifieror the like and is particularly suitable for being used in a wirelesscommunication system.

What is claimed is:
 1. A semiconductor integrated circuit comprising: aplurality of electronic circuits, each of them having an inputconstituted by a single differential signal or a plurality ofdifferential signals and an output of single phase, wherein inputpolarities of a first one of the plurality of electronic circuits and asecond one of the plurality of electronic circuits are inverted, and anoutput terminal of the first electronic circuit and an output terminalof the second electronic circuit are connected to a circuit of theplurality of electronic circuits having a function of suppressing acommon-mode signal component between the two terminals and amplifying adifferential signal, wherein the circuit having the function is composedof a third one of the electronic circuits and a fourth one of theelectronic circuits respectively having two input terminals, a firstoutput terminal for receiving a signal provided by adding an outputsignal from the output terminal of the first electronic circuit and anoutput signal of the third electronic circuit, and a second outputterminal for receiving a signal provided by adding an output signal fromthe output terminal of the second electronic circuit and an outputsignal of the fourth electronic circuit, and wherein the first outputterminal is connected to one of input terminals of the third electroniccircuit, the second output terminal is connected to other input terminalof the third electronic circuit and the second output terminal isconnected to one of input terminals of the fourth electronic circuit andthe first output terminal is connected to other input terminal of thefourth electronic circuit.
 2. The semiconductor integrated circuitaccording to claim 1, wherein when an electronic circuit of theplurality of electronic circuits constituting a constituent elementinputs a plurality of input signals and outputs an output in proportionto a total sum of the inputs.
 3. The semiconductor integrated circuitaccording to claims 1, wherein the electronic circuit constituting theconstituent element is a transconductance circuit.
 4. The semiconductorintegrated circuit according to claim 2, wherein the electronic circuitconstituting the constituent element is a transconductance circuit. 5.The semiconductor integrated circuit according to claim 3, wherein theinput polarities of a first transconductance circuit and a secondtransconductance circuit are inverted, output terminals of a thirdtransconductance circuit and a fourth transconductance circuit areconnected to an output terminal of the first transconductance circuit,an input terminal having a negative polarity of the thirdtransconductance circuit is connected to the output terminal of thefirst transconductance circuit, an input terminal having a positivepolarity of the third transconductance circuit is grounded, an inputterminal having a negative polarity of the fourth transconductancecircuit is connected to an output terminal of the secondtransconductance circuit, an input terminal having a positive polarityof the fourth transconductance circuit is grounded, output terminals ofa fifth and a sixth transconductance circuits are connected to theoutput terminal of the second transconductance circuit, an inputterminal having a negative polarity of the fifth transconductancecircuit is connected to the output terminal of the secondtransconductance circuit, an input terminal having a positive polarityof the fifth transconductance circuit is grounded, an input terminalhaving a negative polarity of the sixth transconductance circuit isconnected to the output terminal of the first transconductance circuitand an input terminal having a positive polarity of the sixthtransconductance circuit is grounded.
 6. The semiconductor integratedcircuit according to claim 4, wherein the input polarities of a firsttransconductance circuit and a second transconductance circuit areinverted, output terminals of a third transconductance circuit and afourth transconductance circuit are connected to an output terminal ofthe first transconductance circuit, an input terminal having a negativepolarity of the third transconductance circuit is connected to theoutput terminal of the first transconductance circuit, an input terminalhaving a positive polarity of the third transconductance circuit isgrounded, an input terminal having a negative polarity of the fourthtransconductance circuit is connected to an output terminal of thesecond transconductance circuit, an input terminal having a positivepolarity of the fourth transconductance circuit is grounded, outputterminals of a fifth and a sixth transconductance circuits are connectedto the output terminal of the second transconductance circuit, an inputterminal having a negative polarity of the fifth transconductancecircuit is connected to the output terminal of the secondtransconductance circuit, an input terminal having a positive polarityof the fifth transconductance circuit is grounded, an input terminalhaving a negative polarity of the sixth transconductance circuit isconnected to the output terminal of the first transconductance circuitand an input terminal having a positive polarity of the sixthtransconductance circuit is grounded.
 7. The semiconductor integratedcircuit according to claim 5, wherein a first terminal of a firstcapacitor is connected to the output terminal of the firsttransconductance circuit, a second terminal of the capacitor isgrounded, a first terminal of a second capacitor is connected to theoutput terminal of the second transconductance circuit and a secondterminal of the capacitor is grounded. 8.The semiconductor integratedcircuit according to claim 6, wherein a first terminal of a firstcapacitor is connected to the output terminal of the firsttransconductance circuit, a second terminal of the capacitor isgrounded, a first terminal of a second capacitor is connected to theoutput terminal of the second transconductance circuit and a secondterminal of the capacitor is grounded.
 9. The semiconductor integratedcircuit according to claim 5, wherein the first transconductance circuitand the second transconductance circuit are replaced by filter circuitseach having a frequency characteristic and having differential inputsand a single phase output.
 10. The semiconductor integrated circuitaccording to claim 6, wherein the first transconductance circuit and thesecond transconductance circuit are replaced by filter circuits eachhaving a frequency characteristic and having differential inputs and asingle phase output.
 11. The semiconductor integrated circuit accordingto claim 7, wherein filters are constituted with the circuit as anintegrator.
 12. The semiconductor integrated circuit according to claim8, wherein filters are constituted with the circuit as an integrator.13. The semiconductor integrated circuit according to claim 3, whereininput polarities of a first transconductance circuit and a secondtransconductance circuit are inverted, a base of a first bipolartransistor is connected to an output terminal of the firsttransconductance circuit, a collector of the first transistor isconnected to the output terminal of the second transconductance circuit,a base of a second bipolar transistor is connected to an output terminalof the second transconductance circuit and a collector of the secondtransistor is connected to the output terminal of the firsttransconductance circuit.
 14. The semiconductor integrated circuitaccording to claim 4, wherein input polarities of a firsttransconductance circuit and a second transconductance circuit areinverted, a base of a first bipolar transistor is connected to an outputterminal of the first transconductance circuit, a collector of the firsttransistor is connected to the output terminal of the secondtransconductance circuit, a base of a second bipolar transistor isconnected to an output terminal of the second transconductance circuitand a collector of the second transistor is connected to the outputterminal of the first transconductance circuit.
 15. The semiconductorintegrated circuit according to claim 13, wherein the first and thesecond bipolar transistors are replaced by field effect transistors. 16.The semiconductor integrated circuit according to claim 14, wherein thefirst and the second bipolar transistors are replaced by field effecttransistors.